1. Field of the Invention
The present invention relates to a vertical power semiconductor device having self turn-off function and to a manufacturing method thereof.
2. Description of the Background Art
First, a conventional semiconductor device will be described.
FIG. 96 is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a first prior art example. Referring to FIG. 96, the first prior art example has an SITh (Static Induction Thyristor). The SITh includes a pin diode porion, a p type gate region 307, a gate electrode layer 309, a cathode electrode 311 and an anode electrode 313.
A pin diode portion has a stacked structure including a p+, anode region 301, an n− region 303 and a cathode region (n+ emitter region) 305. The p type gate region 307 is formed in n− region 303. Gate electrode 309 is electrically connected to p type gate region 307. Cathode electrode 311 is electrically connected to cathode region 305, and anode electrode 313 is electrically connected to p+ anode region 301, respectively.
The SITh can realize on-state by setting gate voltage applied to gate electrode 309 positive. At this time, current flows through pin diode from p+ anode region 301 to the side of cathode region 305.
FIG. 97 is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a second prior art example. Referring to FIG. 97, the second prior art example shows a GTO (Gate Turn-Off) thyristor. The GTO thyristor has a p+ anode region 351, an n− region 353, a p base region 355, a cathode region 357, a gate electrode 359, a cathode electrode 361 and an anode electrode 363.
The p+ anode region 351, n− region 353, p base region 355 and cathode region 357 are stacked successively. The p type base region 355 is electrically connected to gate electrode 359. Cathode electrode 361 is electrically connected to cathode region 357, and anode electrode 363 is electrically connected to p+ anode region 351, respectively.
In this GTO thyristor also, on-state can be realized by setting the gate voltage positive. By setting gate voltage positive, current flows through a pnpn diode from p+ corrector region 351 to the side of cathode region 357.
Both in the first and second prior art examples, off-state can be realized by applying a negative voltage to the gate electrode. When a negative voltage is applied to gate electrode 309 or 359, minority carriers (holes) remaining in the device are extracted from gate electrode 309 or 359. Thus, the main current is cut off.
FIG. 98 is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a third prior art example. Referring to FIG. 98, the third prior art example shows an example of a trench IGBT (Insulated Gate Bipolar Transistor). The trench IGBT includes a p+ collector region 101, n+ buffer region 103, n− region 105, p type base region 107, n+ emitter region 109, a p+ contact region 111, a gate oxide film 115, a gate electrode layer 117, a cathode electrode (emitter) 121 and an anode electrode (collector) 123. On p+ collector region 101, n− region 105 is formed with n+ buffer region 103 interposed. On n− region 105, n+ emitter region 109 and p+ contact region 111 are formed adjacent to each other with p type base region 107 interposed. On the surface where n+ emitter region 109 is formed, there is provided a trench 413.
Trench 413 passes through n+ emitter region 109 and p type base region 107 and reaches n− region 105. The depth Tp of trench 413 from the surface is 3 to 5 μm.
Along inner wall surface of trench 413, gate oxide film 115 is formed. Gate electrode layer 117 is formed to fill the trench 413 and with its upper end projecting from trench 413. Gate electrode layer 117 opposes to n+ emitter region 109, p type base region 107 and n− region 105 with gate oxide film 115 interposed.
Interlayer insulating layer 119 is formed to cover an upper end of gate electrode layer 117. In interlayer insulating layer, there is provided an opening which disposes the surfaces of n+ emitter region 109 and p+ contact region 111. Cathode electrode (emitter) 121 is formed so as to electrically connect n+ emitter region 109 and p+ contact region 111 through the opening. Anode electrode (collector) 123 is formed to be electrically connected to p+ collector region 101.
Hereinafter, the surface of the semiconductor substrate on which cathode electrode 121 is formed will be referred to as a cathode surface or a first main surface, and the surface where anode electrode 123 is formed will be referred to as an anode surface or the second main surface.
A trench MOS gate structure in which gate electrode layer 117 is formed in trench 413 with gate oxide film 115 interposed is manufactured through the following steps.
First, in a semiconductor substrate, a relatively deep trench 413 of about 3 to about 5 μm is formed by common anisotropic dry etching. Sacrificial oxidation or cleaning is performed on the inner wall of trench 413. Thereafter, a silicon thermal oxide film (hereinafter referred to as a gate oxide film) 115 is formed at a temperature from 900° C. to 1000° C. in, for example, vapor ambient (H2O). A polysilicon film doped with an n type impurity such as phosphorous or a polycrystalline silicon film doped with a p type impurity such as boron fills the trench 413. The doped polysilicon film is patterned so that trench 413 is filled and doped polysilicon film is drawn out at least from a porion of trench 413 to the surface of the cathode side. The patterned doped polysilicon film is electrically connected to a gate surface interconnection formed of a metal such as aluminum, provided entirely over the semiconductor device, while insulated from cathode electrode 121.
The method of controlling on-state and off-state in the third prior art example will be described.
On-state is realized by applying a positive (+) voltage to gate electrode 117 while a forward bias is applied between cathode electrode 121-anode electrode 123, that is, while a positive (+) voltage is applied to anode electrode 123 and a negative (−) voltage is applied to cathode electrode 121.
A turn-on process in which the device transits from off-state to the on-state will be described in the following.
When a positive (+) voltage is applied to gate electrode layer 117, an n channel (inverted n region) which is inverted to n type and having very high electron density is generated at p base region 107 near gate oxide film 115. Electrons, which are one of the current carriers (hereinafter referred to as carriers) are injected from n+ emitter region 109 through the n channel to n— region 105, and flow to p+ collector region 101 to which the positive (+) voltage is applied. When the electrons reach p+ collector region 101, holes, which are other current carrier are injected from p+ collector region 101 to n− region 105 and flow to n+ emitter region 109 to which the negative (−) voltage is applied. Thus, the flow reaches the position where the aforementioned n channel is in contact with n− region 105. This process is referred to as storage process, and the time necessary for this process is referred to as storage time (tstorage) or turn-off delay time (td(off)). Power loss during the storage time is so small that it can be neglected, as compared with steady loss, which will be described layer.
Thereafter, from anode electrode 123 and cathode electrode 121, sufficient current carriers are stored in n− region 105 to such an amount that is larger by two or three orders of magnitude than the concentration of semiconductor substrate (1×1012 to 1×1015 cm−3), in accordance with the difference between potentials applied to both electrodes. Accordingly, a low resistance state referred to as conductivity modulation is caused by the hole-electron pairs, thus turn-on is completed. This process is referred to as a rise process, and the time necessary for this process is referred to as rise time (trise). Power loss during this time is approximately the same or larger than the steady loss, which will be described layer later, and constitutes roughly one fourth of the entire loss.
The steady state after the completion of turn-on is referred to as on-state, and the power loss represented by a product of on-state voltage caused by on resistance (effectively, potential difference between both electrodes) and the conduction current is referred to as on-loss or steady loss.
When a positive voltage is applied to gate electrode layer 117, an n+ accumulation region 425a having high electron density is formed along the sidewalls of trench 113, as shown in FIG. 99.
Off-state is realized by applying a negative (−) voltage to gate electrode layer 117, even when forward bias is being applied to anode electrode 123-cathode electrode 121.
A turn off process in which the device transits from on state to off state will be described in the following.
When a negative (−) voltage is applied to gate electrode layer 117, n channel (inverted n region) formed on the side surface of gate electrode layer 117 is eliminated, and supply of electrodes from n+ emitter region 109 to n− region 105 is stopped. The process up to here is referred to as storage process, and the time necessary for this process is referred to as storage time (ts) or turn off delay time (td(off)). The power loss during this time is very small as compared with the turn on loss and the steady loss, and it can be neglected.
As the electron density reduces, the density of electrons which has been introduced to n− region 105 gradually reduces from the vicinity of n+ emitter region 109. In order to maintain charge neutralize condition, holes which have been introduced to n− region 105 also reduce, and p base region 107 and n− region 105 are reversely biased. Consequently, depletion layer begins to extend at the interface between p base region 107 and n− region 105, and tends to have a thickness which corresponds to the applied voltage in the off state between both electrodes. The process up to here is referred to as a fall process, and the time necessary for this process is referred to as fall time (tf). The power loss during this time is approximately the same or larger than the aforementioned turn off loss and steady loss, and it constitutes roughly one fourth of the entire loss.
Further, holes in an electrically neutral region where both carriers remain outside the aforementioned depletion region (p+ collector region 101) pass through the depletion region and extracted through p+ contact region 111 to emitter electrode 121, thus carriers are all eliminated and turn off is completed. This process is referred to tail process, and the time necessary for this process is referred to as tail time (ttail). The power loss during the tail time is referred to as tail loss, which is approximately the same or larger than the turn on loss, loss during the fall time and steady loss, and it constitutes roughly one fourth of the entire loss.
The steady state after the completion of turn off is referred to as off state and power loss caused by the product of leak current in this state and the voltage between both electrodes is referred to as off loss. However, generally it is smaller than other power losses and it can be neglected.
The above described first and second prior art examples relate to current control type devices in which minority carriers are extracted from gate electrodes 309 and 359 to set off-state. Therefore, at the time of turn off, it is necessary to extract a considerable amount of the main current from the gate electrode. When a relatively large current is to be extracted, there will be a large surge current caused by inductance of interconnections or the like, and heat radiation caused by current must also be taken into consideration. Therefore, it becomes necessary to provide a protecting circuit against surge voltage and excessive current, in the circuit for controlling the gate voltage. This makes the gate control circuit complicated. Further, it is possible that the control circuit is thermally destroyed or suffers from thermal runaway because of heat, and hence a cooling mechanism must be provided. This makes the device larger.
A semiconductor device which solves these problems is disclosed in Japanese Patent Laying-Open No. 5-243561. The semiconductor device disclosed in this application will be described as a fourth prior art example.
FIG. 100 is a plan view schematically showing the structure of the semiconductor device in accordance with the fourth prior art example, and FIGS. 101 and 102 are cross sectional views taken along the lines P-P′ and Q-Q′ of FIG. 100, respectively.
Referring to FIGS. 100 to 102, the fourth prior art example shows an electrostatic induction thyristor. On one surface of a high resistance n type base layer 501, a p type emitter layer 503 is formed with an n type buffer layer 502 interposed. On the other surface of n type base layer 501, a plurality of trenches 505 are formed spaced by a small distance from each other. In these trenches 505, gate electrodes 507 are formed embedded, with gate oxide film 506 interposed. At every other region between the trenches 505, n type turn off channel layer 508 is formed. On the surface of turn off channel layer 508, a p type drain layer 509 is formed. At a surface portion sandwiched between p type drain layers 509, an n type source layer 510 is formed.
A cathode electrode 511 is formed to be electrically connected to p type drain layer 509 and n type source layer 510. An anode electrode 512 is formed to be electrically connected to p type emitter layer 503.
In the fourth prior art example, when the positive voltage is applied to gate electrode 507 to raise the potential of n type base layer 501 sandwiched between the trenches 505, electrons are introduced from n type source layer 510, so that the device turns on. Meanwhile, when a negative voltage is applied to a gate electrode layer 507, a p type channel is formed on a side surface of the trench of n type turn off channel layer 508, carriers of n base layer 501 are discharged through p drain layer 509 to cathode electrode 511, and therefore the device turns off.
In the fourth prior art example, the gate electrode 507 has an insulated gate structure. Therefore, in the fourth prior art example, the gate electrode 507b is not of the current control type in which current is directly drawn out from the substrate, but it is of a voltage controlled type in which control is realized by the voltage (gate voltage) applied to the gate electrode.
Since the fourth prior art example is of the voltage controlled type, it is not necessary to extract a large current from gate electrode layer 507 at the time of turn off. Accordingly, it is not necessary to provide a protecting circuit or a cooling mechanism in consideration of surge current and heat caused when large current is extracted. Therefore, the fourth prior art example is advantageous in that the gate control circuit can be simplified.
However, in the fourth prior art example, at the surface region sandwiched between trenches 507 extending parallel to each other as shown in FIG. 100, there are p type drain layer 509 and n type source layer 510 adjacent to each other. Since p type drain layer 509 has a potential barrier with respect to the electrons, the electron current entering the cathode electrode 511 flows only through the portion of n type source layer 510. Therefore, there is inhibiting factor such as partial increase in current density, which results in degraded on characteristics.
In the third prior art example shown in FIG. 98, it is not possible to improve on-state voltage Vf, and hence power consumption of the semiconductor device is considerably large. This will be described in greater detail.
As a method of improving ON voltage (on-state voltage Vf of a diode) which is a basic characteristic of IGBT, there is a method of improving injection efficiency of electrons on the side of the cathode. In order to improve injection efficiency of electrons, it is necessary to increase impurity concentration on the side of the cathode or to increase the effective cathode area. The effective cathode area means the area of a portion (denoted by the solid line in the figure) where n+ region (effective cathode region) including n+ emitter region 109 and storage region 425a is in contact with p type base region 107 and n− region 105.
In the third prior art example, the depth of the trench 413 is 3-5 μm, as already described. Therefore, when a positive voltage is applied to gate electrode layer, extension of the storage layer generated around the trench 113 is limited. Accordingly, it is not possible to ensure the large effective cathode area. This hinders improvement in injection efficiency of electrons on the side of the cathode, and hence ON voltage of IGBT cannot be reduced.